Undisclosed foundry is the second purchaser of ASML’s $400 million second-gen EUV machine

With a higher-resolution sample transferred to a wafer, a foundry won’t must run a wafer via the EUV a second time to print the main points wanted which saves the foundry each money and time. At ASML’s convention name following its newest earnings report, Christophe Fouquet, chief enterprise officer of ASML, stated, “Concerning Excessive-NA, or 0.55 NA EUV, we shipped our first system to a buyer and this method is presently underneath set up. We began to ship the second system this month and its set up can be about to begin.” 

The recipient of the second Excessive-NA EUV to ship is unknown. TSMC, the world’s largest foundry, might be not the unnamed purchaser of the newest Excessive-NA EUV to be ordered. The foundry must purchase one someday, nevertheless it does not appear that it’s interested by making this buy now. In the meantime, ASML is believed to be engaged on the third-generation Hyper-NA EUV with a numerical aperture above .7.

Intel is within the course of of putting in its Twinscan EXE:5000 Excessive-NA EUV which value the corporate about $400 million. Intel will begin utilizing the machine when it begins producing chips with its Intel 14A course of node. By getting a head begin on putting in and utilizing the machine, Intel would possibly seize a bonus in an upcoming three-way battle for course of management between Samsung Foundry, TSMC, and Intel. Intel’s 14A course of node, equal to TSMC and Samsung’s 1.4nm course of nodes, is predicted for use in mass manufacturing someday in 2027 across the identical time that TSMC and Samsung Foundry kick off 1.4nm manufacturing.

When course of nodes decline, so does the scale of the transistors used with these chips. Meaning extra transistors can match inside these elements and the upper a chip’s transistor rely, the extra highly effective and/or energy-efficient a chip is. That is why the Excessive NA EUV is so vital. As course of nodes shrink and extra transistors match inside chips, the circuitry patterns etched on the silicon wafers should be made utilizing a finer decision so as to shoehorn billions of transistors inside these elements.

ASML’s Fouquet says, “The client curiosity for our [High-NA] system lab is excessive as this method will assist each our Logic and Reminiscence clients put together for Excessive-NA insertion into their roadmaps. Relative to 0.33 NA, the 0.55 NA system gives finer decision enabling an virtually 3x improve in transistor density, at an analogous productiveness, in assist of sub-2nm Logic and sub-10nm DRAM nodes.”